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@@ -0,0 +1,613 @@
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+use num_derive::FromPrimitive;
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+
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+#[derive(Debug, Clone, Copy, PartialEq, FromPrimitive)]
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+#[repr(u8)]
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+pub enum Opcode {
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+ Lddw,
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+ Ldxb,
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+ Ldxh,
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+ Ldxw,
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+ Ldxdw,
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+ Stb,
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+ Sth,
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+ Stw,
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+ Stdw,
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+ Stxb,
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+ Stxh,
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+ Stxw,
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+ Stxdw,
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+ Add32,
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+ Add32Imm,
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+ Add32Reg,
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+ Sub32,
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+ Sub32Imm,
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+ Sub32Reg,
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+ Mul32,
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+ Mul32Imm,
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+ Mul32Reg,
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+ Div32,
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+ Div32Imm,
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+ Div32Reg,
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+ Or32,
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+ Or32Imm,
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+ Or32Reg,
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+ And32,
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+ And32Imm,
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+ And32Reg,
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+ Lsh32,
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+ Lsh32Imm,
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+ Lsh32Reg,
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+ Rsh32,
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+ Rsh32Imm,
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+ Rsh32Reg,
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+ Mod32,
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+ Mod32Imm,
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+ Mod32Reg,
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+ Xor32,
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+ Xor32Imm,
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+ Xor32Reg,
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+ Mov32,
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+ Mov32Imm,
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+ Mov32Reg,
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+ Arsh32,
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+ Arsh32Imm,
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+ Arsh32Reg,
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+ Lmul32,
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+ Lmul32Imm,
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+ Lmul32Reg,
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+ Udiv32,
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+ Udiv32Imm,
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+ Udiv32Reg,
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+ Urem32,
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+ Urem32Imm,
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+ Urem32Reg,
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+ Sdiv32,
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+ Sdiv32Imm,
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+ Sdiv32Reg,
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+ Srem32,
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+ Srem32Imm,
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+ Srem32Reg,
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+ Le,
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+ Be,
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+ Add64,
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+ Add64Imm,
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+ Add64Reg,
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+ Sub64,
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+ Sub64Imm,
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+ Sub64Reg,
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+ Mul64,
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+ Mul64Imm,
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+ Mul64Reg,
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+ Div64,
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+ Div64Imm,
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+ Div64Reg,
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+ Or64,
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+ Or64Imm,
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+ Or64Reg,
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+ And64,
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+ And64Imm,
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+ And64Reg,
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+ Lsh64,
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+ Lsh64Imm,
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+ Lsh64Reg,
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+ Rsh64,
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+ Rsh64Imm,
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+ Rsh64Reg,
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+ Mod64,
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+ Mod64Imm,
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+ Mod64Reg,
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+ Xor64,
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+ Xor64Imm,
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+ Xor64Reg,
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+ Mov64,
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+ Mov64Imm,
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+ Mov64Reg,
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+ Arsh64,
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+ Arsh64Imm,
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+ Arsh64Reg,
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+ Hor64Imm,
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+ Lmul64,
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+ Lmul64Imm,
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+ Lmul64Reg,
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+ Uhmul64,
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+ Uhmul64Imm,
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+ Uhmul64Reg,
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+ Udiv64,
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+ Udiv64Imm,
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+ Udiv64Reg,
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+ Urem64,
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+ Urem64Imm,
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+ Urem64Reg,
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+ Shmul64,
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+ Shmul64Imm,
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+ Shmul64Reg,
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+ Sdiv64,
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+ Sdiv64Imm,
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+ Sdiv64Reg,
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+ Srem64,
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+ Srem64Imm,
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+ Srem64Reg,
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+ Neg32,
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+ Neg64,
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+ Ja,
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+ Jeq,
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+ JeqImm,
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+ JeqReg,
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+ Jgt,
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+ JgtImm,
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+ JgtReg,
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+ Jge,
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+ JgeImm,
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+ JgeReg,
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+ Jlt,
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+ JltImm,
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+ JltReg,
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+ Jle,
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+ JleImm,
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+ JleReg,
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+ Jset,
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+ JsetImm,
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+ JsetReg,
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+ Jne,
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+ JneImm,
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+ JneReg,
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+ Jsgt,
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+ JsgtImm,
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+ JsgtReg,
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+ Jsge,
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+ JsgeImm,
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+ JsgeReg,
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+ Jslt,
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+ JsltImm,
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+ JsltReg,
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+ Jsle,
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+ JsleImm,
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+ JsleReg,
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+ Call,
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+ Callx,
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+ Exit,
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+}
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+
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+impl Opcode {
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+ pub fn from_str(s: &str) -> Result<Self, &'static str> {
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+ match s.to_lowercase().as_str() {
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+ "lddw" => Ok(Opcode::Lddw),
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+ "ldxb" => Ok(Opcode::Ldxb),
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+ "ldxh" => Ok(Opcode::Ldxh),
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+ "ldxw" => Ok(Opcode::Ldxw),
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+ "ldxdw" => Ok(Opcode::Ldxdw),
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+ "stb" => Ok(Opcode::Stb),
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+ "sth" => Ok(Opcode::Sth),
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+ "stw" => Ok(Opcode::Stw),
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+ "stdw" => Ok(Opcode::Stdw),
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+ "stxb" => Ok(Opcode::Stxb),
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+ "stxh" => Ok(Opcode::Stxh),
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+ "stxw" => Ok(Opcode::Stxw),
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+ "stxdw" => Ok(Opcode::Stxdw),
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+ "add32" => Ok(Opcode::Add32),
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+ "sub32" => Ok(Opcode::Sub32),
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+ "mul32" => Ok(Opcode::Mul32),
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+ "div32" => Ok(Opcode::Div32),
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+ "or32" => Ok(Opcode::Or32),
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+ "and32" => Ok(Opcode::And32),
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+ "lsh32" => Ok(Opcode::Lsh32),
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+ "rsh32" => Ok(Opcode::Rsh32),
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+ "neg32" => Ok(Opcode::Neg32),
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+ "mod32" => Ok(Opcode::Mod32),
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+ "xor32" => Ok(Opcode::Xor32),
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+ "mov32" => Ok(Opcode::Mov32),
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+ "arsh32" => Ok(Opcode::Arsh32),
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+ "lmul32" => Ok(Opcode::Lmul32),
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+ "udiv32" => Ok(Opcode::Udiv32),
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+ "urem32" => Ok(Opcode::Urem32),
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+ "sdiv32" => Ok(Opcode::Sdiv32),
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+ "srem32" => Ok(Opcode::Srem32),
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+ "le" => Ok(Opcode::Le),
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+ "be" => Ok(Opcode::Be),
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+ "add64" => Ok(Opcode::Add64),
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+ "sub64" => Ok(Opcode::Sub64),
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+ "mul64" => Ok(Opcode::Mul64),
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+ "div64" => Ok(Opcode::Div64),
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+ "or64" => Ok(Opcode::Or64),
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+ "and64" => Ok(Opcode::And64),
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+ "lsh64" => Ok(Opcode::Lsh64),
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+ "rsh64" => Ok(Opcode::Rsh64),
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+ "neg64" => Ok(Opcode::Neg64),
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+ "mod64" => Ok(Opcode::Mod64),
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+ "xor64" => Ok(Opcode::Xor64),
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+ "mov64" => Ok(Opcode::Mov64),
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+ "arsh64" => Ok(Opcode::Arsh64),
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+ "hor64" => Ok(Opcode::Hor64Imm),
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+ "lmul64" => Ok(Opcode::Lmul64),
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+ "uhmul64" => Ok(Opcode::Uhmul64),
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+ "udiv64" => Ok(Opcode::Udiv64),
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+ "urem64" => Ok(Opcode::Urem64),
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+ "shmul64" => Ok(Opcode::Shmul64),
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+ "sdiv64" => Ok(Opcode::Sdiv64),
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+ "srem64" => Ok(Opcode::Srem64),
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+ "ja" => Ok(Opcode::Ja),
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+ "jeq" => Ok(Opcode::Jeq),
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+ "jgt" => Ok(Opcode::Jgt),
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+ "jge" => Ok(Opcode::Jge),
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+ "jlt" => Ok(Opcode::Jlt),
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+ "jle" => Ok(Opcode::Jle),
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+ "jset" => Ok(Opcode::Jset),
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+ "jne" => Ok(Opcode::Jne),
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+ "jsgt" => Ok(Opcode::Jsgt),
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+ "jsge" => Ok(Opcode::Jsge),
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+ "jslt" => Ok(Opcode::Jslt),
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+ "jsle" => Ok(Opcode::Jsle),
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+ "call" => Ok(Opcode::Call),
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+ "callx" => Ok(Opcode::Callx),
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+ "exit" => Ok(Opcode::Exit),
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+ _ => Err("Invalid opcode"),
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+ }
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+ }
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+
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+ pub fn from_u8(u: u8) -> Option<Self> {
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+ match u {
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+ 0x18 => Some(Opcode::Lddw),
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+ 0x71 => Some(Opcode::Ldxb),
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+ 0x69 => Some(Opcode::Ldxh),
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+ 0x61 => Some(Opcode::Ldxw),
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+ 0x79 => Some(Opcode::Ldxdw),
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+ 0x72 => Some(Opcode::Stb),
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+ 0x6a => Some(Opcode::Sth),
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+ 0x62 => Some(Opcode::Stw),
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+ 0x7a => Some(Opcode::Stdw),
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+ 0x73 => Some(Opcode::Stxb),
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+ 0x6b => Some(Opcode::Stxh),
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+ 0x63 => Some(Opcode::Stxw),
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+ 0x7b => Some(Opcode::Stxdw),
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+ 0x04 => Some(Opcode::Add32Imm),
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+ 0x0c => Some(Opcode::Add32Reg),
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+ 0x14 => Some(Opcode::Sub32Imm),
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+ 0x1c => Some(Opcode::Sub32Reg),
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+ 0x24 => Some(Opcode::Mul32Imm),
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+ 0x2c => Some(Opcode::Mul32Reg),
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+ 0x34 => Some(Opcode::Div32Imm),
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+ 0x3c => Some(Opcode::Div32Reg),
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+ 0x44 => Some(Opcode::Or32Imm),
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+ 0x4c => Some(Opcode::Or32Reg),
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+ 0x54 => Some(Opcode::And32Imm),
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+ 0x5c => Some(Opcode::And32Reg),
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+ 0x64 => Some(Opcode::Lsh32Imm),
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+ 0x6c => Some(Opcode::Lsh32Reg),
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+ 0x74 => Some(Opcode::Rsh32Imm),
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+ 0x7c => Some(Opcode::Rsh32Reg),
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+ 0x94 => Some(Opcode::Mod32Imm),
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+ 0x9c => Some(Opcode::Mod32Reg),
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+ 0xa4 => Some(Opcode::Xor32Imm),
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+ 0xac => Some(Opcode::Xor32Reg),
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+ 0xb4 => Some(Opcode::Mov32Imm),
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+ 0xbc => Some(Opcode::Mov32Reg),
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+ 0xc4 => Some(Opcode::Arsh32Imm),
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+ 0xcc => Some(Opcode::Arsh32Reg),
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+ 0x86 => Some(Opcode::Lmul32Imm),
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+ 0x8e => Some(Opcode::Lmul32Reg),
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+ 0x46 => Some(Opcode::Udiv32Imm),
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+ 0x4e => Some(Opcode::Udiv32Reg),
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+ 0x66 => Some(Opcode::Urem32Imm),
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+ 0x6e => Some(Opcode::Urem32Reg),
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+ 0xc6 => Some(Opcode::Sdiv32Imm),
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+ 0xce => Some(Opcode::Sdiv32Reg),
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+ 0xe6 => Some(Opcode::Srem32Imm),
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+ 0xee => Some(Opcode::Srem32Reg),
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+ 0xd4 => Some(Opcode::Le),
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+ 0xdc => Some(Opcode::Be),
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+ 0x07 => Some(Opcode::Add64Imm),
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+ 0x0f => Some(Opcode::Add64Reg),
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+ 0x17 => Some(Opcode::Sub64Imm),
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+ 0x1f => Some(Opcode::Sub64Reg),
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+ 0x27 => Some(Opcode::Mul64Imm),
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+ 0x2f => Some(Opcode::Mul64Reg),
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+ 0x37 => Some(Opcode::Div64Imm),
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+ 0x3f => Some(Opcode::Div64Reg),
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+ 0x47 => Some(Opcode::Or64Imm),
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+ 0x4f => Some(Opcode::Or64Reg),
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+ 0x57 => Some(Opcode::And64Imm),
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+ 0x5f => Some(Opcode::And64Reg),
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+ 0x67 => Some(Opcode::Lsh64Imm),
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+ 0x6f => Some(Opcode::Lsh64Reg),
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+ 0x77 => Some(Opcode::Rsh64Imm),
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+ 0x7f => Some(Opcode::Rsh64Reg),
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+ 0x97 => Some(Opcode::Mod64Imm),
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+ 0x9f => Some(Opcode::Mod64Reg),
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+ 0xa7 => Some(Opcode::Xor64Imm),
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+ 0xaf => Some(Opcode::Xor64Reg),
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+ 0xb7 => Some(Opcode::Mov64Imm),
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+ 0xbf => Some(Opcode::Mov64Reg),
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+ 0xc7 => Some(Opcode::Arsh64Imm),
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+ 0xcf => Some(Opcode::Arsh64Reg),
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+ 0xf7 => Some(Opcode::Hor64Imm),
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+ 0x96 => Some(Opcode::Lmul64Imm),
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+ 0x9e => Some(Opcode::Lmul64Reg),
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+ 0x36 => Some(Opcode::Uhmul64Imm),
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+ 0x3e => Some(Opcode::Uhmul64Reg),
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+ 0x56 => Some(Opcode::Udiv64Imm),
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+ 0x5e => Some(Opcode::Udiv64Reg),
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+ 0x76 => Some(Opcode::Urem64Imm),
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+ 0x7e => Some(Opcode::Urem64Reg),
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+ 0xb6 => Some(Opcode::Shmul64Imm),
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+ 0xbe => Some(Opcode::Shmul64Reg),
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+ 0xd6 => Some(Opcode::Sdiv64Imm),
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+ 0xde => Some(Opcode::Sdiv64Reg),
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+ 0xf6 => Some(Opcode::Srem64Imm),
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+ 0xfe => Some(Opcode::Srem64Reg),
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+ 0x84 => Some(Opcode::Neg32),
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+ 0x87 => Some(Opcode::Neg64),
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+ 0x05 => Some(Opcode::Ja),
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+ 0x15 => Some(Opcode::JeqImm),
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+ 0x1d => Some(Opcode::JeqReg),
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+ 0x25 => Some(Opcode::JgtImm),
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+ 0x2d => Some(Opcode::JgtReg),
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+ 0x35 => Some(Opcode::JgeImm),
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+ 0x3d => Some(Opcode::JgeReg),
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+ 0xa5 => Some(Opcode::JltImm),
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+ 0xad => Some(Opcode::JltReg),
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+ 0xb5 => Some(Opcode::JleImm),
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+ 0xbd => Some(Opcode::JleReg),
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+ 0x45 => Some(Opcode::JsetImm),
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+ 0x4d => Some(Opcode::JsetReg),
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+ 0x55 => Some(Opcode::JneImm),
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+ 0x5d => Some(Opcode::JneReg),
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+ 0x65 => Some(Opcode::JsgtImm),
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+ 0x6d => Some(Opcode::JsgtReg),
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+ 0x75 => Some(Opcode::JsgeImm),
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+ 0x7d => Some(Opcode::JsgeReg),
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+ 0xc5 => Some(Opcode::JsltImm),
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+ 0xcd => Some(Opcode::JsltReg),
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+ 0xd5 => Some(Opcode::JsleImm),
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+ 0xdd => Some(Opcode::JsleReg),
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+ 0x85 => Some(Opcode::Call),
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+ 0x8d => Some(Opcode::Callx),
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+ 0x95 => Some(Opcode::Exit),
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+ _ => None,
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+ }
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+ }
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+
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+ pub fn to_bytecode(&self) -> u8 {
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+ match self {
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+ Opcode::Lddw => 0x18,
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+ Opcode::Ldxb => 0x71,
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+ Opcode::Ldxh => 0x69,
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+ Opcode::Ldxw => 0x61,
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+ Opcode::Ldxdw => 0x79,
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+ Opcode::Stb => 0x72,
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+ Opcode::Sth => 0x6a,
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+ Opcode::Stw => 0x62,
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+ Opcode::Stdw => 0x7a,
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+ Opcode::Stxb => 0x73,
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+ Opcode::Stxh => 0x6b,
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+ Opcode::Stxw => 0x63,
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+ Opcode::Stxdw => 0x7b,
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+ // Opcode::Add32 => 0x04,
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+ Opcode::Add32Imm => 0x04,
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+ Opcode::Add32Reg => 0x0c,
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+ // Opcode::Sub32 => 0x14,
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+ Opcode::Sub32Imm => 0x14,
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|
|
+ Opcode::Sub32Reg => 0x1c,
|
|
|
+ // Opcode::Mul32 => 0x24,
|
|
|
+ Opcode::Mul32Imm => 0x24,
|
|
|
+ Opcode::Mul32Reg => 0x2c,
|
|
|
+ // Opcode::Div32 => 0x34,
|
|
|
+ Opcode::Div32Imm => 0x34,
|
|
|
+ Opcode::Div32Reg => 0x3c,
|
|
|
+ // Opcode::Or32 => 0x44,
|
|
|
+ Opcode::Or32Imm => 0x44,
|
|
|
+ Opcode::Or32Reg => 0x4c,
|
|
|
+ // Opcode::And32 => 0x54,
|
|
|
+ Opcode::And32Imm => 0x54,
|
|
|
+ Opcode::And32Reg => 0x5c,
|
|
|
+ // Opcode::Lsh32 => 0x64,
|
|
|
+ Opcode::Lsh32Imm => 0x64,
|
|
|
+ Opcode::Lsh32Reg => 0x6c,
|
|
|
+ // Opcode::Rsh32 => 0x74,
|
|
|
+ Opcode::Rsh32Imm => 0x74,
|
|
|
+ Opcode::Rsh32Reg => 0x7c,
|
|
|
+ // Opcode::Mod32 => 0x94,
|
|
|
+ Opcode::Mod32Imm => 0x94,
|
|
|
+ Opcode::Mod32Reg => 0x9c,
|
|
|
+ // Opcode::Xor32 => 0xa4,
|
|
|
+ Opcode::Xor32Imm => 0xa4,
|
|
|
+ Opcode::Xor32Reg => 0xac,
|
|
|
+ // Opcode::Mov32 => 0xb4,
|
|
|
+ Opcode::Mov32Imm => 0xb4,
|
|
|
+ Opcode::Mov32Reg => 0xbc,
|
|
|
+ // Opcode::Arsh32 => 0xc4,
|
|
|
+ Opcode::Arsh32Imm => 0xc4,
|
|
|
+ Opcode::Arsh32Reg => 0xcc,
|
|
|
+ // Opcode::Lmul32 => 0x86,
|
|
|
+ Opcode::Lmul32Imm => 0x86,
|
|
|
+ Opcode::Lmul32Reg => 0x8e,
|
|
|
+ // Opcode::Udiv32 => 0x46,
|
|
|
+ Opcode::Udiv32Imm => 0x46,
|
|
|
+ Opcode::Udiv32Reg => 0x4e,
|
|
|
+ // Opcode::Urem32 => 0x66,
|
|
|
+ Opcode::Urem32Imm => 0x66,
|
|
|
+ Opcode::Urem32Reg => 0x6e,
|
|
|
+ // Opcode::Sdiv32 => 0xc6,
|
|
|
+ Opcode::Sdiv32Imm => 0xc6,
|
|
|
+ Opcode::Sdiv32Reg => 0xce,
|
|
|
+ // Opcode::Srem32 => 0xe6,
|
|
|
+ Opcode::Srem32Imm => 0xe6,
|
|
|
+ Opcode::Srem32Reg => 0xee,
|
|
|
+ Opcode::Le => 0xd4,
|
|
|
+ Opcode::Be => 0xdc,
|
|
|
+ // Opcode::Add64 => 0x07,
|
|
|
+ Opcode::Add64Imm => 0x07,
|
|
|
+ Opcode::Add64Reg => 0x0f,
|
|
|
+ // Opcode::Sub64 => 0x17,
|
|
|
+ Opcode::Sub64Imm => 0x17,
|
|
|
+ Opcode::Sub64Reg => 0x1f,
|
|
|
+ // Opcode::Mul64 => 0x27,
|
|
|
+ Opcode::Mul64Imm => 0x27,
|
|
|
+ Opcode::Mul64Reg => 0x2f,
|
|
|
+ // Opcode::Div64 => 0x37,
|
|
|
+ Opcode::Div64Imm => 0x37,
|
|
|
+ Opcode::Div64Reg => 0x3f,
|
|
|
+ // Opcode::Or64 => 0x47,
|
|
|
+ Opcode::Or64Imm => 0x47,
|
|
|
+ Opcode::Or64Reg => 0x4f,
|
|
|
+ // Opcode::And64 => 0x57,
|
|
|
+ Opcode::And64Imm => 0x57,
|
|
|
+ Opcode::And64Reg => 0x5f,
|
|
|
+ // Opcode::Lsh64 => 0x67,
|
|
|
+ Opcode::Lsh64Imm => 0x67,
|
|
|
+ Opcode::Lsh64Reg => 0x6f,
|
|
|
+ // Opcode::Rsh64 => 0x77,
|
|
|
+ Opcode::Rsh64Imm => 0x77,
|
|
|
+ Opcode::Rsh64Reg => 0x7f,
|
|
|
+ // Opcode::Mod64 => 0x97,
|
|
|
+ Opcode::Mod64Imm => 0x97,
|
|
|
+ Opcode::Mod64Reg => 0x9f,
|
|
|
+ // Opcode::Xor64 => 0xa7,
|
|
|
+ Opcode::Xor64Imm => 0xa7,
|
|
|
+ Opcode::Xor64Reg => 0xaf,
|
|
|
+ // Opcode::Mov64 => 0xb7,
|
|
|
+ Opcode::Mov64Imm => 0xb7,
|
|
|
+ Opcode::Mov64Reg => 0xbf,
|
|
|
+ // Opcode::Arsh64 => 0xc7,
|
|
|
+ Opcode::Arsh64Imm => 0xc7,
|
|
|
+ Opcode::Arsh64Reg => 0xcf,
|
|
|
+ Opcode::Hor64Imm => 0xf7,
|
|
|
+ // Opcode::Lmul64 => 0x87,
|
|
|
+ Opcode::Lmul64Imm => 0x96,
|
|
|
+ Opcode::Lmul64Reg => 0x9e,
|
|
|
+ // Opcode::Uhmul64 => 0x36,
|
|
|
+ Opcode::Uhmul64Imm => 0x36,
|
|
|
+ Opcode::Uhmul64Reg => 0x3e,
|
|
|
+ // Opcode::Udiv64 => 0x56,
|
|
|
+ Opcode::Udiv64Imm => 0x56,
|
|
|
+ Opcode::Udiv64Reg => 0x5e,
|
|
|
+ // Opcode::Urem64 => 0x76,
|
|
|
+ Opcode::Urem64Imm => 0x76,
|
|
|
+ Opcode::Urem64Reg => 0x7e,
|
|
|
+ // Opcode::Shmul64 => 0xb6,
|
|
|
+ Opcode::Shmul64Imm => 0xb6,
|
|
|
+ Opcode::Shmul64Reg => 0xbe,
|
|
|
+ // Opcode::Sdiv64 => 0xd6,
|
|
|
+ Opcode::Sdiv64Imm => 0xd6,
|
|
|
+ Opcode::Sdiv64Reg => 0xde,
|
|
|
+ // Opcode::Srem64 => 0xf6,
|
|
|
+ Opcode::Srem64Imm => 0xf6,
|
|
|
+ Opcode::Srem64Reg => 0xfe,
|
|
|
+ Opcode::Neg32 => 0x84,
|
|
|
+ Opcode::Neg64 => 0x87,
|
|
|
+ Opcode::Ja => 0x05,
|
|
|
+ // Opcode::Jeq => 0x15,
|
|
|
+ Opcode::JeqImm => 0x15,
|
|
|
+ Opcode::JeqReg => 0x1d,
|
|
|
+ // Opcode::Jgt => 0x25,
|
|
|
+ Opcode::JgtImm => 0x25,
|
|
|
+ Opcode::JgtReg => 0x2d,
|
|
|
+ // Opcode::Jge => 0x35,
|
|
|
+ Opcode::JgeImm => 0x35,
|
|
|
+ Opcode::JgeReg => 0x3d,
|
|
|
+ // Opcode::Jlt => 0xa5,
|
|
|
+ Opcode::JltImm => 0xa5,
|
|
|
+ Opcode::JltReg => 0xad,
|
|
|
+ // Opcode::Jle => 0xb5,
|
|
|
+ Opcode::JleImm => 0xb5,
|
|
|
+ Opcode::JleReg => 0xbd,
|
|
|
+ // Opcode::Jset => 0x45,
|
|
|
+ Opcode::JsetImm => 0x45,
|
|
|
+ Opcode::JsetReg => 0x4d,
|
|
|
+ // Opcode::Jne => 0x55,
|
|
|
+ Opcode::JneImm => 0x55,
|
|
|
+ Opcode::JneReg => 0x5d,
|
|
|
+ // Opcode::Jsgt => 0x65,
|
|
|
+ Opcode::JsgtImm => 0x65,
|
|
|
+ Opcode::JsgtReg => 0x6d,
|
|
|
+ // Opcode::Jsge => 0x75,
|
|
|
+ Opcode::JsgeImm => 0x75,
|
|
|
+ Opcode::JsgeReg => 0x7d,
|
|
|
+ // Opcode::Jslt => 0xc5,
|
|
|
+ Opcode::JsltImm => 0xc5,
|
|
|
+ Opcode::JsltReg => 0xcd,
|
|
|
+ // Opcode::Jsle => 0xd5,
|
|
|
+ Opcode::JsleImm => 0xd5,
|
|
|
+ Opcode::JsleReg => 0xdd,
|
|
|
+ Opcode::Call => 0x85,
|
|
|
+ Opcode::Callx => 0x8d,
|
|
|
+ Opcode::Exit => 0x95,
|
|
|
+
|
|
|
+ _ => 0x00,
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ pub fn to_str(&self) -> &'static str {
|
|
|
+ match self {
|
|
|
+ Opcode::Lddw => "lddw",
|
|
|
+ Opcode::Ldxb => "ldxb",
|
|
|
+ Opcode::Ldxh => "ldxh",
|
|
|
+ Opcode::Ldxw => "ldxw",
|
|
|
+ Opcode::Ldxdw => "ldxdw",
|
|
|
+ Opcode::Stb => "stb",
|
|
|
+ Opcode::Sth => "sth",
|
|
|
+ Opcode::Stw => "stw",
|
|
|
+ Opcode::Stdw => "stdw",
|
|
|
+ Opcode::Stxb => "stxb",
|
|
|
+ Opcode::Stxh => "stxh",
|
|
|
+ Opcode::Stxw => "stxw",
|
|
|
+ Opcode::Stxdw => "stxdw",
|
|
|
+ Opcode::Add32 | Opcode::Add32Imm | Opcode::Add32Reg => "add32",
|
|
|
+ Opcode::Sub32 | Opcode::Sub32Imm | Opcode::Sub32Reg => "sub32",
|
|
|
+ Opcode::Mul32 | Opcode::Mul32Imm | Opcode::Mul32Reg => "mul32",
|
|
|
+ Opcode::Div32 | Opcode::Div32Imm | Opcode::Div32Reg => "div32",
|
|
|
+ Opcode::Or32 | Opcode::Or32Imm | Opcode::Or32Reg => "or32",
|
|
|
+ Opcode::And32 | Opcode::And32Imm | Opcode::And32Reg => "and32",
|
|
|
+ Opcode::Lsh32 | Opcode::Lsh32Imm | Opcode::Lsh32Reg => "lsh32",
|
|
|
+ Opcode::Rsh32 | Opcode::Rsh32Imm | Opcode::Rsh32Reg => "rsh32",
|
|
|
+ Opcode::Neg32 => "neg32",
|
|
|
+ Opcode::Mod32 | Opcode::Mod32Imm | Opcode::Mod32Reg => "mod32",
|
|
|
+ Opcode::Xor32 | Opcode::Xor32Imm | Opcode::Xor32Reg => "xor32",
|
|
|
+ Opcode::Mov32 | Opcode::Mov32Imm | Opcode::Mov32Reg => "mov32",
|
|
|
+ Opcode::Arsh32 | Opcode::Arsh32Imm | Opcode::Arsh32Reg => "arsh32",
|
|
|
+ Opcode::Lmul32 | Opcode::Lmul32Imm | Opcode::Lmul32Reg => "lmul32",
|
|
|
+ Opcode::Udiv32 | Opcode::Udiv32Imm | Opcode::Udiv32Reg => "udiv32",
|
|
|
+ Opcode::Urem32 | Opcode::Urem32Imm | Opcode::Urem32Reg => "urem32",
|
|
|
+ Opcode::Sdiv32 | Opcode::Sdiv32Imm | Opcode::Sdiv32Reg => "sdiv32",
|
|
|
+ Opcode::Srem32 | Opcode::Srem32Imm | Opcode::Srem32Reg => "srem32",
|
|
|
+ Opcode::Le => "le",
|
|
|
+ Opcode::Be => "be",
|
|
|
+ Opcode::Add64 | Opcode::Add64Imm | Opcode::Add64Reg => "add64",
|
|
|
+ Opcode::Sub64 | Opcode::Sub64Imm | Opcode::Sub64Reg => "sub64",
|
|
|
+ Opcode::Mul64 | Opcode::Mul64Imm | Opcode::Mul64Reg => "mul64",
|
|
|
+ Opcode::Div64 | Opcode::Div64Imm | Opcode::Div64Reg => "div64",
|
|
|
+ Opcode::Or64 | Opcode::Or64Imm | Opcode::Or64Reg => "or64",
|
|
|
+ Opcode::And64 | Opcode::And64Imm | Opcode::And64Reg => "and64",
|
|
|
+ Opcode::Lsh64 | Opcode::Lsh64Imm | Opcode::Lsh64Reg => "lsh64",
|
|
|
+ Opcode::Rsh64 | Opcode::Rsh64Imm | Opcode::Rsh64Reg => "rsh64",
|
|
|
+ Opcode::Neg64 => "neg64",
|
|
|
+ Opcode::Mod64 | Opcode::Mod64Imm | Opcode::Mod64Reg => "mod64",
|
|
|
+ Opcode::Xor64 | Opcode::Xor64Imm | Opcode::Xor64Reg => "xor64",
|
|
|
+ Opcode::Mov64 | Opcode::Mov64Imm | Opcode::Mov64Reg => "mov64",
|
|
|
+ Opcode::Arsh64 | Opcode::Arsh64Imm | Opcode::Arsh64Reg => "arsh64",
|
|
|
+ Opcode::Hor64Imm => "hor64",
|
|
|
+ Opcode::Lmul64 | Opcode::Lmul64Imm | Opcode::Lmul64Reg => "lmul64",
|
|
|
+ Opcode::Uhmul64 | Opcode::Uhmul64Imm | Opcode::Uhmul64Reg => "uhmul64",
|
|
|
+ Opcode::Udiv64 | Opcode::Udiv64Imm | Opcode::Udiv64Reg => "udiv64",
|
|
|
+ Opcode::Urem64 | Opcode::Urem64Imm | Opcode::Urem64Reg => "urem64",
|
|
|
+ Opcode::Shmul64 | Opcode::Shmul64Imm | Opcode::Shmul64Reg => "shmul64",
|
|
|
+ Opcode::Sdiv64 | Opcode::Sdiv64Imm | Opcode::Sdiv64Reg => "sdiv64",
|
|
|
+ Opcode::Srem64 | Opcode::Srem64Imm | Opcode::Srem64Reg => "srem64",
|
|
|
+ Opcode::Ja | Opcode::Jeq | Opcode::JeqImm | Opcode::JeqReg => "jeq",
|
|
|
+ Opcode::Jgt | Opcode::JgtImm | Opcode::JgtReg => "jgt",
|
|
|
+ Opcode::Jge | Opcode::JgeImm | Opcode::JgeReg => "jge",
|
|
|
+ Opcode::Jlt | Opcode::JltImm | Opcode::JltReg => "jlt",
|
|
|
+ Opcode::Jle | Opcode::JleImm | Opcode::JleReg => "jle",
|
|
|
+ Opcode::Jset | Opcode::JsetImm | Opcode::JsetReg => "jset",
|
|
|
+ Opcode::Jne | Opcode::JneImm | Opcode::JneReg => "jne",
|
|
|
+ Opcode::Jsgt | Opcode::JsgtImm | Opcode::JsgtReg => "jsgt",
|
|
|
+ Opcode::Jsge | Opcode::JsgeImm | Opcode::JsgeReg => "jsge",
|
|
|
+ Opcode::Jslt | Opcode::JsltImm | Opcode::JsltReg => "jslt",
|
|
|
+ Opcode::Jsle | Opcode::JsleImm | Opcode::JsleReg => "jsle",
|
|
|
+ Opcode::Call | Opcode::Callx => "call",
|
|
|
+ Opcode::Exit => "exit",
|
|
|
+ }
|
|
|
+ }
|
|
|
+ pub fn to_string(&self) -> String {
|
|
|
+ self.to_str().to_string()
|
|
|
+ }
|
|
|
+}
|
Claire Fan