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@@ -0,0 +1,388 @@
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+use core::str;
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+use std::fmt::Display;
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+
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+use serde::{Deserialize, Serialize};
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+
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+use crate::errors::EZBpfError;
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+
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+#[repr(u8)]
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+#[derive(Clone, Debug, Serialize, Deserialize, PartialEq, Eq)]
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+pub enum OpCode {
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+ Lddw = 0x18,
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+ Ldxb = 0x71,
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+ Ldxh = 0x69,
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+ Ldxw = 0x61,
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+ Ldxdw = 0x79,
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+ Stb = 0x72,
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+ Sth = 0x6a,
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+ Stw = 0x62,
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+ Stdw = 0x7a,
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+ Stxb = 0x73,
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+ Stxh = 0x6b,
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+ Stxw = 0x63,
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+ Stxdw = 0x7b,
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+ Add32Imm = 0x04,
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+ Add32Reg = 0x0c,
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+ Sub32Imm = 0x14,
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+ Sub32Reg = 0x1c,
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+ Mul32Imm = 0x24,
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+ Mul32Reg = 0x2c,
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+ Div32Imm = 0x34,
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+ Div32Reg = 0x3c,
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+ Or32Imm = 0x44,
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+ Or32Reg = 0x4c,
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+ And32Imm = 0x54,
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+ And32Reg = 0x5c,
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+ Lsh32Imm = 0x64,
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+ Lsh32Reg = 0x6c,
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+ Rsh32Imm = 0x74,
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+ Rsh32Reg = 0x7c,
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+ Neg32 = 0x84,
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+ Mod32Imm = 0x94,
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+ Mod32Reg = 0x9c,
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+ Xor32Imm = 0xa4,
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+ Xor32Reg = 0xac,
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+ Mov32Imm = 0xb4,
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+ Mov32Reg = 0xbc,
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+ Arsh32Imm = 0xc4,
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+ Arsh32Reg = 0xcc,
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+ Lmul32Imm = 0x86,
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+ Lmul32Reg = 0x8e,
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+ Udiv32Imm = 0x46,
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+ Udiv32Reg = 0x4e,
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+ Urem32Imm = 0x66,
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+ Urem32Reg = 0x6e,
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+ Sdiv32Imm = 0xc6,
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+ Sdiv32Reg = 0xce,
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+ Srem32Imm = 0xe6,
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+ Srem32Reg = 0xee,
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+ Le = 0xd4,
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+ Be = 0xdc,
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+ Add64Imm = 0x07,
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+ Add64Reg = 0x0f,
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+ Sub64Imm = 0x17,
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+ Sub64Reg = 0x1f,
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+ Mul64Imm = 0x27,
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+ Mul64Reg = 0x2f,
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+ Div64Imm = 0x37,
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+ Div64Reg = 0x3f,
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+ Or64Imm = 0x47,
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+ Or64Reg = 0x4f,
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+ And64Imm = 0x57,
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+ And64Reg = 0x5f,
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+ Lsh64Imm = 0x67,
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+ Lsh64Reg = 0x6f,
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+ Rsh64Imm = 0x77,
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+ Rsh64Reg = 0x7f,
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+ Neg64 = 0x87,
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+ Mod64Imm = 0x97,
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+ Mod64Reg = 0x9f,
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+ Xor64Imm = 0xa7,
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+ Xor64Reg = 0xaf,
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+ Mov64Imm = 0xb7,
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+ Mov64Reg = 0xbf,
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+ Arsh64Imm = 0xc7,
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+ Arsh64Reg = 0xcf,
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+ Hor64Imm = 0xf7,
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+ Lmul64Imm = 0x96,
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+ Lmul64Reg = 0x9e,
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+ Uhmul64Imm = 0x36,
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+ Uhmul64Reg = 0x3e,
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+ Udiv64Imm = 0x56,
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+ Udiv64Reg = 0x5e,
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+ Urem64Imm = 0x76,
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+ Urem64Reg = 0x7e,
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+ Shmul64Imm = 0xb6,
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+ Shmul64Reg = 0xbe,
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+ Sdiv64Imm = 0xd6,
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+ Sdiv64Reg = 0xde,
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+ Srem64Imm = 0xf6,
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+ Srem64Reg = 0xfe,
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+ Ja = 0x05,
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+ JeqImm = 0x15,
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+ JeqReg = 0x1d,
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+ JgtImm = 0x25,
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+ JgtReg = 0x2d,
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+ JgeImm = 0x35,
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+ JgeReg = 0x3d,
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+ JltImm = 0xa5,
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+ JltReg = 0xad,
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+ JleImm = 0xb5,
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+ JleReg = 0xbd,
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+ JsetImm = 0x45,
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+ JsetReg = 0x4d,
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+ JneImm = 0x55,
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+ JneReg = 0x5d,
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+ JsgtImm = 0x65,
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+ JsgtReg = 0x6d,
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+ JsgeImm = 0x75,
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+ JsgeReg = 0x7d,
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+ JsltImm = 0xc5,
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+ JsltReg = 0xcd,
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+ JsleImm = 0xd5,
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+ JsleReg = 0xdd,
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+ Call = 0x85,
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+ Callx = 0x8d,
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+ Exit = 0x95,
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+}
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+
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+impl Display for OpCode {
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+ fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
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+ f.write_str(Into::<&str>::into(self.clone()))
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+ }
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+}
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+
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+impl TryFrom<u8> for OpCode {
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+ type Error = EZBpfError;
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+
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+ fn try_from(value: u8) -> Result<Self, Self::Error> {
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+ Ok(match value {
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+ 0x18 => OpCode::Lddw,
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+ 0x71 => OpCode::Ldxb,
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+ 0x69 => OpCode::Ldxh,
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+ 0x61 => OpCode::Ldxw,
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+ 0x79 => OpCode::Ldxdw,
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+ 0x72 => OpCode::Stb,
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+ 0x6a => OpCode::Sth,
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+ 0x62 => OpCode::Stw,
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+ 0x7a => OpCode::Stdw,
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+ 0x73 => OpCode::Stxb,
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+ 0x6b => OpCode::Stxh,
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+ 0x63 => OpCode::Stxw,
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+ 0x7b => OpCode::Stxdw,
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+ 0x04 => OpCode::Add32Imm,
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+ 0x0c => OpCode::Add32Reg,
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+ 0x14 => OpCode::Sub32Imm,
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+ 0x1c => OpCode::Sub32Reg,
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+ 0x24 => OpCode::Mul32Imm,
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+ 0x2c => OpCode::Mul32Reg,
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+ 0x34 => OpCode::Div32Imm,
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+ 0x3c => OpCode::Div32Reg,
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+ 0x44 => OpCode::Or32Imm,
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+ 0x4c => OpCode::Or32Reg,
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+ 0x54 => OpCode::And32Imm,
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+ 0x5c => OpCode::And32Reg,
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+ 0x64 => OpCode::Lsh32Imm,
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+ 0x6c => OpCode::Lsh32Reg,
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+ 0x74 => OpCode::Rsh32Imm,
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+ 0x7c => OpCode::Rsh32Reg,
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+ 0x84 => OpCode::Neg32,
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+ 0x94 => OpCode::Mod32Imm,
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+ 0x9c => OpCode::Mod32Reg,
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+ 0xa4 => OpCode::Xor32Imm,
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+ 0xac => OpCode::Xor32Reg,
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+ 0xb4 => OpCode::Mov32Imm,
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+ 0xbc => OpCode::Mov32Reg,
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+ 0xc4 => OpCode::Arsh32Imm,
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+ 0xcc => OpCode::Arsh32Reg,
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+ 0x86 => OpCode::Lmul32Imm,
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+ 0x8e => OpCode::Lmul32Reg,
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+ 0x46 => OpCode::Udiv32Imm,
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+ 0x4e => OpCode::Udiv32Reg,
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+ 0x66 => OpCode::Urem32Imm,
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+ 0x6e => OpCode::Urem32Reg,
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+ 0xc6 => OpCode::Sdiv32Imm,
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+ 0xce => OpCode::Sdiv32Reg,
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+ 0xe6 => OpCode::Srem32Imm,
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+ 0xee => OpCode::Srem32Reg,
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+ 0xd4 => OpCode::Le,
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+ 0xdc => OpCode::Be,
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+ 0x07 => OpCode::Add64Imm,
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+ 0x0f => OpCode::Add64Reg,
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+ 0x17 => OpCode::Sub64Imm,
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+ 0x1f => OpCode::Sub64Reg,
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+ 0x27 => OpCode::Mul64Imm,
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+ 0x2f => OpCode::Mul64Reg,
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+ 0x37 => OpCode::Div64Imm,
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+ 0x3f => OpCode::Div64Reg,
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+ 0x47 => OpCode::Or64Imm,
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+ 0x4f => OpCode::Or64Reg,
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+ 0x57 => OpCode::And64Imm,
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+ 0x5f => OpCode::And64Reg,
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+ 0x67 => OpCode::Lsh64Imm,
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+ 0x6f => OpCode::Lsh64Reg,
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+ 0x77 => OpCode::Rsh64Imm,
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+ 0x7f => OpCode::Rsh64Reg,
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+ 0x87 => OpCode::Neg64,
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+ 0x97 => OpCode::Mod64Imm,
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+ 0x9f => OpCode::Mod64Reg,
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+ 0xa7 => OpCode::Xor64Imm,
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+ 0xaf => OpCode::Xor64Reg,
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+ 0xb7 => OpCode::Mov64Imm,
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+ 0xbf => OpCode::Mov64Reg,
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+ 0xc7 => OpCode::Arsh64Imm,
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+ 0xcf => OpCode::Arsh64Reg,
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+ 0xf7 => OpCode::Hor64Imm,
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+ 0x96 => OpCode::Lmul64Imm,
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+ 0x9e => OpCode::Lmul64Reg,
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+ 0x36 => OpCode::Uhmul64Imm,
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+ 0x3e => OpCode::Uhmul64Reg,
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+ 0x56 => OpCode::Udiv64Imm,
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+ 0x5e => OpCode::Udiv64Reg,
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+ 0x76 => OpCode::Urem64Imm,
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+ 0x7e => OpCode::Urem64Reg,
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+ 0xb6 => OpCode::Shmul64Imm,
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+ 0xbe => OpCode::Shmul64Reg,
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+ 0xd6 => OpCode::Sdiv64Imm,
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+ 0xde => OpCode::Sdiv64Reg,
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+ 0xf6 => OpCode::Srem64Imm,
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+ 0xfe => OpCode::Srem64Reg,
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+ 0x05 => OpCode::Ja,
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+ 0x15 => OpCode::JeqImm,
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+ 0x1d => OpCode::JeqReg,
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+ 0x25 => OpCode::JgtImm,
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+ 0x2d => OpCode::JgtReg,
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+ 0x35 => OpCode::JgeImm,
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+ 0x3d => OpCode::JgeReg,
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+ 0xa5 => OpCode::JltImm,
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+ 0xad => OpCode::JltReg,
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+ 0xb5 => OpCode::JleImm,
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+ 0xbd => OpCode::JleReg,
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+ 0x45 => OpCode::JsetImm,
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+ 0x4d => OpCode::JsetReg,
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+ 0x55 => OpCode::JneImm,
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+ 0x5d => OpCode::JneReg,
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+ 0x65 => OpCode::JsgtImm,
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+ 0x6d => OpCode::JsgtReg,
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+ 0x75 => OpCode::JsgeImm,
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+ 0x7d => OpCode::JsgeReg,
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+ 0xc5 => OpCode::JsltImm,
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+ 0xcd => OpCode::JsltReg,
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+ 0xd5 => OpCode::JsleImm,
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+ 0xdd => OpCode::JsleReg,
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+ 0x85 => OpCode::Call,
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+ 0x8d => OpCode::Callx,
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+ 0x95 => OpCode::Exit,
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+ _ => return Err(EZBpfError::InvalidOpcode),
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+ })
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+ }
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+}
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+
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+impl From<OpCode> for u8 {
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+ fn from(val: OpCode) -> Self {
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+ val as u8
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+ }
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+}
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+
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+impl From<OpCode> for &str {
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+ fn from(val: OpCode) -> Self {
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+ match val {
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+ OpCode::Lddw => "lddw",
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+ OpCode::Ldxb => "ldxb",
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+ OpCode::Ldxh => "ldxh",
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+ OpCode::Ldxw => "ldxw",
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+ OpCode::Ldxdw => "ldxdw",
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+ OpCode::Stb => "stb",
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+ OpCode::Sth => "sth",
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+ OpCode::Stw => "stw",
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+ OpCode::Stdw => "stdw",
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+ OpCode::Stxb => "stxb",
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+ OpCode::Stxh => "stxh",
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+ OpCode::Stxw => "stxw",
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+ OpCode::Stxdw => "stxdw",
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+ OpCode::Add32Imm => "add32",
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+ OpCode::Add32Reg => "add32",
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+ OpCode::Sub32Imm => "sub32",
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+ OpCode::Sub32Reg => "sub32",
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+ OpCode::Mul32Imm => "mul32",
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+ OpCode::Mul32Reg => "mul32",
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+ OpCode::Div32Imm => "div32",
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+ OpCode::Div32Reg => "div32",
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+ OpCode::Or32Imm => "or32",
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+ OpCode::Or32Reg => "or32",
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+ OpCode::And32Imm => "and32",
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+ OpCode::And32Reg => "and32",
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+ OpCode::Lsh32Imm => "lsh32",
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|
|
|
|
+ OpCode::Lsh32Reg => "lsh32",
|
|
|
|
|
+ OpCode::Rsh32Imm => "rsh32",
|
|
|
|
|
+ OpCode::Rsh32Reg => "rsh32",
|
|
|
|
|
+ OpCode::Neg32 => "neg32",
|
|
|
|
|
+ OpCode::Mod32Imm => "mod32",
|
|
|
|
|
+ OpCode::Mod32Reg => "mod32",
|
|
|
|
|
+ OpCode::Xor32Imm => "xor32",
|
|
|
|
|
+ OpCode::Xor32Reg => "xor32",
|
|
|
|
|
+ OpCode::Mov32Imm => "mov32",
|
|
|
|
|
+ OpCode::Mov32Reg => "mov32",
|
|
|
|
|
+ OpCode::Arsh32Imm => "arsh32",
|
|
|
|
|
+ OpCode::Arsh32Reg => "arsh32",
|
|
|
|
|
+ OpCode::Lmul32Imm => "lmul32",
|
|
|
|
|
+ OpCode::Lmul32Reg => "lmul32",
|
|
|
|
|
+ OpCode::Udiv32Imm => "udiv32",
|
|
|
|
|
+ OpCode::Udiv32Reg => "udiv32",
|
|
|
|
|
+ OpCode::Urem32Imm => "urem32",
|
|
|
|
|
+ OpCode::Urem32Reg => "urem32",
|
|
|
|
|
+ OpCode::Sdiv32Imm => "sdiv32",
|
|
|
|
|
+ OpCode::Sdiv32Reg => "sdiv32",
|
|
|
|
|
+ OpCode::Srem32Imm => "srem32",
|
|
|
|
|
+ OpCode::Srem32Reg => "srem32",
|
|
|
|
|
+ OpCode::Le => "le",
|
|
|
|
|
+ OpCode::Be => "be",
|
|
|
|
|
+ OpCode::Add64Imm => "add64",
|
|
|
|
|
+ OpCode::Add64Reg => "add64",
|
|
|
|
|
+ OpCode::Sub64Imm => "sub64",
|
|
|
|
|
+ OpCode::Sub64Reg => "sub64",
|
|
|
|
|
+ OpCode::Mul64Imm => "mul64",
|
|
|
|
|
+ OpCode::Mul64Reg => "mul64",
|
|
|
|
|
+ OpCode::Div64Imm => "div64",
|
|
|
|
|
+ OpCode::Div64Reg => "div64",
|
|
|
|
|
+ OpCode::Or64Imm => "or64",
|
|
|
|
|
+ OpCode::Or64Reg => "or64",
|
|
|
|
|
+ OpCode::And64Imm => "and64",
|
|
|
|
|
+ OpCode::And64Reg => "and64",
|
|
|
|
|
+ OpCode::Lsh64Imm => "lsh64",
|
|
|
|
|
+ OpCode::Lsh64Reg => "lsh64",
|
|
|
|
|
+ OpCode::Rsh64Imm => "rsh64",
|
|
|
|
|
+ OpCode::Rsh64Reg => "rsh64",
|
|
|
|
|
+ OpCode::Neg64 => "neg64",
|
|
|
|
|
+ OpCode::Mod64Imm => "mod64",
|
|
|
|
|
+ OpCode::Mod64Reg => "mod64",
|
|
|
|
|
+ OpCode::Xor64Imm => "xor64",
|
|
|
|
|
+ OpCode::Xor64Reg => "xor64",
|
|
|
|
|
+ OpCode::Mov64Imm => "mov64",
|
|
|
|
|
+ OpCode::Mov64Reg => "mov64",
|
|
|
|
|
+ OpCode::Arsh64Imm => "arsh64",
|
|
|
|
|
+ OpCode::Arsh64Reg => "arsh64",
|
|
|
|
|
+ OpCode::Hor64Imm => "hor64",
|
|
|
|
|
+ OpCode::Lmul64Imm => "lmul64",
|
|
|
|
|
+ OpCode::Lmul64Reg => "lmul64",
|
|
|
|
|
+ OpCode::Uhmul64Imm => "uhmul64",
|
|
|
|
|
+ OpCode::Uhmul64Reg => "uhmul64",
|
|
|
|
|
+ OpCode::Udiv64Imm => "udiv64",
|
|
|
|
|
+ OpCode::Udiv64Reg => "udiv64",
|
|
|
|
|
+ OpCode::Urem64Imm => "urem64",
|
|
|
|
|
+ OpCode::Urem64Reg => "urem64",
|
|
|
|
|
+ OpCode::Shmul64Imm => "shmul64",
|
|
|
|
|
+ OpCode::Shmul64Reg => "shmul64",
|
|
|
|
|
+ OpCode::Sdiv64Imm => "sdiv64",
|
|
|
|
|
+ OpCode::Sdiv64Reg => "sdiv64",
|
|
|
|
|
+ OpCode::Srem64Imm => "srem64",
|
|
|
|
|
+ OpCode::Srem64Reg => "srem64",
|
|
|
|
|
+ OpCode::Ja => "ja",
|
|
|
|
|
+ OpCode::JeqImm => "jeq",
|
|
|
|
|
+ OpCode::JeqReg => "jeq",
|
|
|
|
|
+ OpCode::JgtImm => "jgt",
|
|
|
|
|
+ OpCode::JgtReg => "jgt",
|
|
|
|
|
+ OpCode::JgeImm => "jge",
|
|
|
|
|
+ OpCode::JgeReg => "jge",
|
|
|
|
|
+ OpCode::JltImm => "jlt",
|
|
|
|
|
+ OpCode::JltReg => "jlt",
|
|
|
|
|
+ OpCode::JleImm => "jle",
|
|
|
|
|
+ OpCode::JleReg => "jle",
|
|
|
|
|
+ OpCode::JsetImm => "jset",
|
|
|
|
|
+ OpCode::JsetReg => "jset",
|
|
|
|
|
+ OpCode::JneImm => "jne",
|
|
|
|
|
+ OpCode::JneReg => "jne",
|
|
|
|
|
+ OpCode::JsgtImm => "jsgt",
|
|
|
|
|
+ OpCode::JsgtReg => "jsgt",
|
|
|
|
|
+ OpCode::JsgeImm => "jsge",
|
|
|
|
|
+ OpCode::JsgeReg => "jsge",
|
|
|
|
|
+ OpCode::JsltImm => "jslt",
|
|
|
|
|
+ OpCode::JsltReg => "jslt",
|
|
|
|
|
+ OpCode::JsleImm => "jsle",
|
|
|
|
|
+ OpCode::JsleReg => "jsle",
|
|
|
|
|
+ OpCode::Call => "call",
|
|
|
|
|
+ OpCode::Callx => "callx",
|
|
|
|
|
+ OpCode::Exit => "exit",
|
|
|
|
|
+ }
|
|
|
|
|
+ }
|
|
|
|
|
+}
|